The present invention relates to integrated circuits, and more particularly to fabrication of dielectric used to insulate a gate from another element of the integrated circuit.
FIG. 1 illustrates a flash memory cell 110 having a number of gates. The cell is described in U.S. Pat. No. 6,057,575 issued May 2, 2000 to Jenq. The cell is formed in and over a semiconductor substrate 120. Silicon dioxide 130 is thermally grown on substrate 120. Select gate 140 is formed on oxide 130. Silicon dioxide 150 is thermally grown on a region of substrate 120 not covered by the select gate. ONO 154 (a sandwich of a layer of silicon dioxide, a layer of silicon nitride, and another layer of silicon dioxide) is formed on select gate 140. Floating gate 160 is formed on dielectric layers 150, 154. A portion of floating gate 160 overlies the select gate 140.
ONO layer 164 is formed on the floating and select gates. Control gate element 170 is formed on ONO 164. The control gate overlies the floating gate 160 and the select gate 140.
N+ source and drain regions 174, 178 are formed in substrate 120.
Select gate 140 controls the conductivity of a channel region underlying the select gate in substrate 120. Floating gate 160 (together with control gate 170) controls a channel region under the floating gate. Both channel regions are part of a continuous channel region extending between the source/drain regions 174, 178.
FIG. 2 shows a circuit diagram of a memory array of cells 110. This is a NOR array. Each cell is shown schematically as a floating gate transistor and a select transistor connected in series. Select gate lines 140, control gate lines 170, and source lines 178 extend in the row direction (Y direction) throughout the array. Each select gate line 140 provides the select gates for one row of the array. Each control gate line 170 provides the control gates for one row. Each source line 178 is connected to source/drain regions 178 of two adjacent rows (here the same numeral 178 is used for the source lines and the source/drain regions). Bitlines 180 extend in the column direction (X direction). Each bitline 180 is connected to the regions 174 of two adjacent columns.
A cell 110 is programmed by hot electron injection from the cell's channel region (the P type region in substrate 120 below the cell's floating and select gates) to floating gate 160. The cell is erased by Fowler-Nordheim tunneling of electrons from floating gate 160 to source line region 178. The cell is read by sensing a current on the corresponding bitline region 174.
It is desirable to develop simple, inexpensive fabrication processes to insulate the select gate 140 from other elements in the integrated circuit. It is also desirable to provide simple and inexpensive gate insulation processes for integrated circuits that may or may not include nonvolatile memory.